An associative memory system called Content Addressable Memory (CAM) has been developed to permit its memory cells to be referenced by their contents. Thus CAM has found use in lookup table implementations such as cache memory subsystems and is now rapidly finding use in networking system applications such as network address translation, and other applications such as pattern recognition, and data compression. CAM's most valuable feature is its ability to perform a fast search operation in which search data is compared with data stored within the CAM. Typically search data is loaded onto search lines and compared with stored words in the CAM. During a search-and-compare operation, the CAM performs a fully parallel search and generates a match or mismatch signal associated with each stored word, indicating whether the search word matches a stored word or not.
To allow this fast parallel comparison between all stored words to a single search word, each CAM word contains dedicated search hardware. Each CAM cell contains additional bit-comparison transistors, in addition to a conventional storage element, which is typically implemented as a Static Random Access Memory (SRAM) cell or a Dynamic Random Access Memory (DRAM) cell. This added circuitry is combined across the word with a match-line (ML) to produce a match or mismatch signal for each CAM word.
Moreover, this search hardware allows the entire contents of the CAM memory to be searched in a single memory cycle.
Thus, in contrast to standard memory (SRAM or DRAM) which would typically require 1 K clock cycles to complete a search of a 1 K words memory, a CAM has the ability to search all entries simultaneously in a single clock cycle.
Unfortunately, as technology scales to submicron geometries, random device variation (RDV) is becoming more prominent. RDV of parameters such as transistor length, transistor width and transistor threshold voltage could be significant even in identically designed neighboring devices. The effects of RDV are especially evident in the design of semiconductor memories. Because most memories rely on sense amplifiers to detect small voltage signals on largely capacitive array lines, RDV in the memory cells as well as sense-amplifier devices can produce incorrect results. To improve reliability, memory designers tune their sensing circuits conservatively, thereby trading off performance in order to maintain a large sensing margin for reliable operation.
In advanced technologies (i.e. 100 nm and smaller gate geometry) RDV is becoming a major bottleneck for improving performance. As device variation increases, timing uncertainty for signal arrival and data capture increases, requiring larger data capture margins, and therefore limiting performance.
Due to its single-ended nature, the ML sensing performed during the CAM search operation is even more sensitive to RDV than the differential sensing used in the SRAM read circuitry. Thus, to maintain reliable operation, most ML sensing schemes employ full-swing sensing which is both slow and power-inefficient.